1. Field of the Invention
The present invention relates, in general, to a semiconductor chip scale package and method of producing such a package and, more particularly, to an improvement in such a package and method for providing a semiconductor package, with a package size being similar to or slightly larger than a semiconductor chip, without deteriorating the conventionally-expected operational function of the package.
2. Description of the Prior Art
In accordance with the recent trend of compactness, lightness and smallness of semiconductor-electronic appliances such as electronic home appliances, communications appliances and computers, it is necessary to reduce the size and weight of semiconductor packages without deteriorating the operational function of the packages.
However, in known quad flat semiconductor packages, it is very difficult to reduce the plane size or the area of each package due to the outer leads extending from four side surfaces of each package. In an effort to overcome the problem caused by the known quad flat packages, BGA (ball grid array) semiconductor packages are proposed and used. Known BGA packages reduce the size of packages by about 20% in comparison with the known quad flat packages. However, the known BGA packages are problematic in that the size or area of each package is several times as large as the area of a semiconductor chip used in the package. Therefore, the known BGA packages regrettably fail to completely achieve the recent trend of compactness, lightness and smallness of semiconductor-electronic appliances.
In order to overcome the problems caused by the known quad flat and BGA packages, a flip chip package with a reduced size is proposed. The known flip chip packages more effectively reduce the size of the packages in comparison with the other types of known packages as they are produced through a flip chip mounting process. An example of a typical flip chip package is shown in FIG. 6. As shown in this drawing, the flip chip mounting process of forming a flip chip package is processed as follows. That is, a plurality of bumps 31 are formed on the bond pad (not shown) which is positioned on the top surface of a semiconductor chip 10. After forming the bumps 31 on the bond pad, the bond pad with the bumps 31 is turned over prior to welding the bumps 31 to the copper pattern 203 of a printed circuit board 200 at a position where the pattern 203 is free from a solder mask 202 and is thereby exposed to the atmosphere. Thereafter, an epoxy resin 40 fills in the junction between the chip 10 and the pattern 203, with the bumps 31 being set in the resin 40, thus forming a flip chip package. In the flip chip package, the bumps 31 electrically connect the bond pad of the chip 10 to a plurality of solder balls 30 through the copper pattern 203. The solder balls 30, which are spaced apart from the chip 10 by predetermined distances, are used as signal input and output terminals of the package. In FIG. 6, the reference numeral 201 denotes a polymer resin substrate of the PCB 200.
However, the known flip chip packages are problematic in that they are remarkably larger than the semiconductor chips used in them thus failing to achieve the recent trend of compactness, lightness and smallness of semiconductor-electronic appliances.